1. Field of Invention
The present invention relates to the built-in-self-test of embedded memories, and more particularly, to methods of generating multiple sets of inputs from a single seed set of inputs enabling high-speed testing by a lower speed BIST circuit.
2. Background of Invention
Embedded memories require special test solutions due to the unique characteristics of memory circuits. Typically, integrated circuits (ICs) that contain embedded memories also contain a Built-In-Self-Test circuit (BIST) which is used to enable the testing of the memory by generating command, address, and data (CAD) patterns for exercising the memory. Using the BIST for this purpose enables the use of an external logic tester to test the logic portion of the IC as well as the embedded memory.
Testing embedded memories at their highest operating speed (that is the shortest command cycle time) requires that the CAD patterns be generated at that high operating speed. However, as memory speeds increase, it becomes difficult for a BIST to calculate the CAD pattern in this short cycle time, particularly given the circuit area constraints placed on the BIST.
As embedded memory performance and complexity continues to increase, BIST testing at application speeds also becomes more important; hence, novel schemes that support increased BIST performance, while still maintaining BIST flexibility and minimizing design schedule and chip area are of great value. An architecture that allows for a single BIST that can test a diverse range of memory types and sizes at a number of different performance points would be advantageous.